1. Field of the Invention
The invention relates generally to methods for fabricating semiconductor memory devices, and in particular to an auxiliary transistor structure used in semiconductor device fabrication.
2. Background of the invention
Dynamic Random Access Memory (DRAM) chips are distinguished by having a regular arrangement in a memory cell array assigned to a memory area. In the course of a transition from the memory area to the periphery, which may be provided with logic circuits, for example, the regular arrangement is interrupted. Topology differences lead to irregularities both during a lithographic imaging and during a subsequent etching process.
In order to avoid these difficulties, auxiliary transistor structures are provided at the edge of the memory cell array. The auxiliary transistor structures are based on the transistor structures in the memory cell array but have no functionality. In general, the auxiliary transistor structures comprise a weakly p-doped zone on which a gate structure with gate oxide and gate conductor is provided, and such transistors have an influence on lithography and etching processes but no relevance whatsoever to the electrical circuit. The auxiliary transistor structures are usually positioned as a frame at the edge of the memory cell array. During the processing of the frame, however, contaminants often occur in the gate oxide and enable an electrically conductive connection of gate conductor and p-doped zone. Such gate oxide breakdowns are harmful since, on the one hand, a standby current may increase appreciably and, on the other hand, locally at the edge of the memory cell array, a potential of the p-type zone may change and thus adversely affect the performance of the DRAM memory chip.
In accordance with the prior art, a loss of yield that has arisen in the production of DRAM memory chips on account of deficiencies during the processing of auxiliary structures has hitherto been accepted. A mechanism which might have contributed to keeping the loss of yield within tolerable limits is the formation of a parasitic diode. Since the gate conductor assigned to the auxiliary transistor structures is situated on very weakly doped silicon, the pure p-doped zone, at locations at which the gate oxide is not present on account of processing inaccuracies, a metal-semiconductor compound may be formed in the form of a diode which is similar to a Schottky Diode. If the gate conductor is at a more positive potential than the p-doped zone, the diode causes blocking and thus prevents possible leakage current between gate conductor and p-doped zone. By contrast, if the gate conductor is at a more negative potential than the p-doped zone, the diode opens.
Since a trend toward evermore negative reverse voltages of the n-type field-effect application transistors is apparent in more recent DRAM memory chip designs, the latter are coming closer and closer into a voltage range in which the parasitic diode opens. In conjunction with the opened parasitic diode, gate oxide breakdowns occur repeatedly and cause an appreciable leakage current between gate conductor and p-doped zone. Typical potentials of the p-doped zone are 0 or −0.1 V, for example. The reverse voltage of the application transistors may typically be at −0.5 V. Given such a combination, the parasitic diode may already open completely and bring about an undesirable leakage current.
In light of the forgoing it will be appreciated that a need exists to reduce leakage in DRAM memories.